VHDL record type in SV

VHDL-type_pkg：
library ieee;
use ieee.std_logic_1164.all;
package type_pkg is 
    type type_grp is record
        s1 : std_logic;
        s2 : std_logic_vector(1 downto 0);
        s3 : std_logic_vector(2 downto 0);
        s4 : std_logic_vector(3 downto 0);
    end record;
end type_pkg;

package body type_pkg is
-- empty
end type_pkg;
VHDL-test：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.type_pkg.all;
entity test is 
port (
    d : in type_grp
);
end test;

architecture behav of test is
signal tmp : type_grp;
begin
    tmp <= d;
end behav;
SystemVerilog-PART：
`timescale 1 ns / 1 ps
module top_tb;
import type_pkg::*;
type_grp d_set;
initial begin
       d_set.s1 = 1'b0;
       d_set.s2 = 2'b10;
       d_set.s3 = 3'b110;
       d_set.s4 = 4'b1110;
    #2 d_set.s1 = 1'b1;
       d_set.s2 = 2'b01;
       d_set.s3 = 3'b001;
       d_set.s4 = 4'b0001;
    #2 $stop;
end

test u_dut(d_set);
endmodule // top_tb

【编译仿真命令】

a 编译

% vcom -mixedsvvh type_pkg.vhd

% vcom test.vhd

% vlog -sv top_tv.v

b 析构

% vsim -novopt top_tb

c 仿真

% run

【仿真结果】 

对于VHDL record接口类型在SystemVerilog中例化的问题，虽然通过一些EDA厂商提供的EDA工具通过增加特定的编译选项可以解决，但是并不是所有的EDA工具都像Mentor的QuestaSim这样提供有解决措施（编译选项”-mixedsvvh”），所以在具体的VHDL record接口例化时建议对具有record接口的VHDL代码外包一层，该包装层实现对record接口的拆分。

2 SystemVerilog中定义的struct在VHDL中例化

【示例】

SystemVerilog - type_pkg：
package type_pkg;
    typedef struct {
        logic       s1;
        logic [1:0] s2;
        logic [2:0] s3;
        logic [3:0] s4;
    }type_grp;
endpackage // type_pkg;
SystemVerilog - test：
import type_pkg::*;
module sv_mod(input type_grp sv_port);
// blank
endmodule // sv_mode
VHDL - PART：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- 对于type_pkg库的引用不能忽略掉
library work;
use work.type_pkg.all;

entity top_tb is
end top_tb;

architecture behav of top_tb is

component sv_mod
port (
    sv_port : in type_grp
);
end component;

signal sig : type_grp;

begin
process begin
    sig.s1 <= '1';
    sig.s2 <= "10";
    sig.s3 <= "100";
    sig.s4 <= "1000";
    wait for 10 ns;
    sig.s1 <= '0';
    sig.s2 <= "01";
    sig.s3 <= "001";
    sig.s4 <= "0001";
    wait for 10 ns;
    wait;    
end process;

u_dut : sv_mod
port map(
    sv_port => sig
);
end behav;

【编译仿真命令】

a 编译

% vlog -mixedsvvh -sv type_pkg.sv

% vlog -sv sv_mod.sv

% vcom top_tb.vhd

b 析构

% vsim -novopt top_tb

c 仿真

% run

【仿真结果】 

示例中type_pkg.sv中定义的struct如果直接在top_tb.vhd中引用将会导致编译错误，为此在对type_pkg.sv进行编译时需要加上“-mixedsvvh”选项，尽管这样还需要在top_tb.vhd中指明type_pkg.sv编译的逻辑库，否则还是会存在找不到struct数据结构的问题。

下面是“-mixedsvvh”在QuestaSim中的详细说明，大家可以根据自己的设计需要求进行使用。

【针对VHDL设计的vcom编译使用的mixedsvvh】

· -mixedsvvh [b | l | r ][i]

(optional) Facilitates using VHDL packages at the SystemVerilog-VHDL boundary of a mixed-language design. When you compile a VHDL package with -mixedsvvh, the package can be included in a SystemVerilog design as if it were defined in SystemVerilog itself.

Executing -mixedsvvh without arguments compiles VHDL vectors in the following ways:

· VHDL bit_vectors are treated as SystemVerilog bit vectors.

· VHDL std_logic_vectors, std_ulogic_vectors, and vl_logic_vectors are treated as SystemVerilog logic vectors.

b — treats all scalars and vectors in the package as SystemVerilog bit type

l — treats all scalars and vectors in the package as SystemVerilog logic type

r — treats all scalars and vectors in the package as SystemVerilog reg type

i — ignores the range specified with VHDL integer types. Can be specified together with b, l, or r, spaces are not allowed between arguments.

 【针对SystemVerilog设计的vlog编译使用的mixedsvvh】

· -mixedsvvh [b | s | v]

(optional) Facilitates using SystemVerilog packages at the SystemVerilog-VHDL boundary of a mixed-language design. When you compile a SystemVerilog package with -mixedsvvh, the package can be included in a VHDL design as if it were defined in VHDL itself.

b — treats all scalars/vectors in the package as VHDL bit/bit_vector

s — treats all scalars/vectors in the package as VHDL std_logic/std_logic_vector

v — treats all scalars/vectors in the package as VHDL vl_logic/vl_logic_vector