题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
reg flag;
reg [7:0]data_lock;
always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
		data_lock <= 8'd0;
	else if(valid_in && ~flag)
		data_lock <= data_in;
end
always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
		flag <= 1'd0;
	else if(valid_in)
		flag <= ~flag ;
end
always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
		valid_out <= 1'd0;
	else if(valid_in && flag)
		valid_out <= 1'd1;
	else 
		valid_out <= 1'd0;
end
always@(posedge clk or negedge rst_n)begin
	if(~rst_n)
		data_out <= 8'd0;
	else if(valid_in && flag)
		data_out <= {data_lock,data_in};
end
endmodule

这个比前面的都简单，不是很懂牛客这个出题顺序