题解 | #时钟切换#

`timescale 1ns/1ns

module huawei6(
    input wire clk0  ,
    input wire clk1  ,
    input wire rst  ,
    input wire sel ,
    output reg clk_out
);
//*************code***********//
reg ff1,ff2;
    always@(negedge clk0 or negedge rst) begin
        if(!rst)
            ff1 <= 0;
        else
            ff1 <= ~ff2&sel;
    end
    always@(negedge clk1 or negedge rst) begin
        if(!rst)
            ff2 <= 0;
        else
            ff2 <= ~ff1&~sel;
    end
    always@(*) clk_out = ff2&clk0 | ff1&clk1;

//*************code***********//
endmodule