`timescale 1ns/1ns module triffic_light ( input rst_n, //异位复位信号,低电平有效 input clk, //时钟信号 input pass_request, output wire[7:0]clock, output reg red, output reg yellow, output reg green ); parameter IDLE = 4'b0001, GREEN = 4'b0010, YELLOW = 4'b0100, RED = 4'b1000; reg [3:0] STATE; reg [5:0] cnt; always...