题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );

    parameter IDLE   = 4'b0001,
              GREEN  = 4'b0010,
              YELLOW = 4'b0100,
              RED    = 4'b1000;

    reg [3:0] STATE;
    reg [5:0] cnt;

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            STATE <= IDLE;
            cnt <= 6'd10;
            red <= 1'b0;
            yellow <= 1'b0;
            green <= 1'b0;
        end
        else begin
            case(STATE)
                IDLE: begin
                    if(cnt == 6'd8) begin
                        cnt <= 6'd10;
                        STATE <= RED;
                        red <= 1'b1;
                    end
                    else begin
                        cnt <= cnt - 1'b1;
                        STATE <= IDLE;
                    end
                end
                RED: begin
                    if(cnt == 6'd1) begin
                        cnt <= 6'd5;
                        red <= 1'b0;
                        yellow <= 1'b1;
                        STATE <= YELLOW;
                    end
                    else begin
                        cnt <= cnt - 1'b1;
                        STATE <= RED;
                    end
                end
                YELLOW: begin
                    if(cnt == 6'd1) begin
                        cnt <= 6'd60;
                        yellow <= 1'b0;
                        green <= 1'b1;
                        STATE <= GREEN;
                    end
                    else begin
                        cnt <= cnt - 1'b1;
                        STATE <= YELLOW;
                    end
                end
                GREEN: begin
                    if(cnt == 6'd1) begin
                        cnt <= 6'd10;
                        red <= 1'b1;
                        green <= 1'b0;
                        STATE <= RED;
                    end
                    else begin
                        STATE <= GREEN;
                        if(pass_request) begin
                            if(cnt <= 6'd10)
                                cnt <= cnt - 1'b1;
                            else begin
                                cnt <= 6'd10;
                            end
                        end
                        else   
                            cnt <= cnt - 1'b1;
                    end
                end
                default: begin
                    red <= 1'b0;
                    yellow <= 1'b0;
                    green <= 1'b0;
                    cnt <= 6'd10;
                    STATE <= IDLE;
                end
            endcase
        end
    end

    assign clock = {2'b00,cnt};
	
endmodule