题解 | 输入序列不连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

    reg [3:0] reg_a;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            reg_a <= 4'b0; // Reset the register
        end
        else if (data_valid) begin
            reg_a <= {reg_a[2:0], data}; // Shift in the new bit 'data'
        end
    end

    always @(*) begin
        if (data_valid == 1 && reg_a == 4'b0110) begin
            match <= 1'b1; // Match found for the sequence "0110"
        end
        else begin
            match <= 1'b0; // No match
        end
    end
endmodule