题解 | 根据状态转移表实现时序电路

`timescale 1ns/1ns

module seq_circuit(
    input                A   ,
    input                clk ,
    input                rst_n,

    output   wire        Y   
);
    
    reg [1:0] state;
    localparam S0 = 2'b00,
               S1 = 2'b01,
               S2 = 2'b10,
               S3 = 2'b11;

    // always @(posedge clk or negedge rst_n) begin
    //     if (!rst_n) begin
    //         Y <= 1'b0;
    //     end
    //     else if (state == S3) begin
    //         Y <= 1'b1;
    //     end
    // end

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state <= S0;
        end else begin
            case (state)
                S0: if (A) state <= S3; else state <= S1;
                S1: if (A) state <= S0; else state <= S2;
                S2: if (A) state <= S1; else state <= S3;
                S3: if (A) state <= S2; else state <= S0;
                default: state <= S0;
            endcase
        end
    end

    assign Y = (state == S3) ? 1'b1 : 1'b0;
endmodule