题解 | 单端口RAM

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
parameter DEPTH = 128;
parameter WIDTH = 4;
reg [WIDTH-1:0] RAM [DEPTH-1:0];
//写入RAM
always@(posedge clk) 
    RAM[addr] <= enb ? w_data : RAM[addr];   

//读取RAM
assign r_data = enb ? 0 : RAM[addr];
//*************code***********//
endmodule

module testbench();
reg rst;
reg enb;
reg [6:0] addr;
reg [3:0] w_data;
wire [3:0] r_data;
	reg clk=0;
	always #1 clk = ~clk;  //题目要求是周期5ns，但是时间有点长，牛客跑不动，我就改成2了
// A testbench   
//end 
integer i;   
  initial begin
    $dumpfile("out.vcd");
    // This will dump all signal, which may not be useful
    //$dumpvars;
    // dumping only this module
    //$dumpvars(1, testbench);
    // dumping only these variable
    // the first number (level) is actually useless
    $dumpvars(0, testbench);
     rst = 0;
    enb = 0;
    w_data = 0;
    addr = 0;
    #2;
    rst = 1;
    enb = 1;
    for(i=0;i<17;i++)//节约时间，这里随便写了一个值
      @(posedge clk) begin
        addr <= i;
        w_data <=(w_data==4'd15) ? 0 : (w_data + 1);
      end
    #2;
    enb = 0;
    for(i=0;i < 13; i++)//节约时间，这里随便写了一个值
    @(posedge clk)
      addr <= i;  
    #2;
    $finish;
end  

RAM_1port RAM_1port_tb(
  .clk(clk),
  .rst(rst),
  .enb(enb),
  .addr(addr),
  .w_data(w_data),
  .r_data(r_data)
); 

https://blog.csdn.net/Loudrs/article/details/130956115?fromshare=blogdetail&sharetype=blogdetail&sharerId=130956115&sharerefer=PC&sharesource=&sharefrom=from_link

这篇文章讲解了单端口、伪双端口、真双端口的区别以及相应代码，可以看看