题解 | 不重叠序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

reg [5:0] data_reg;
reg [2:0] cnt;

always@(posedge clk or negedge rst_n)
if(!rst_n)begin
	cnt <= 'd0;
end
else if(cnt == 3'd5)begin
	cnt <= 3'd0;
end
else begin
	cnt <= cnt + 1'b1;
end

always@(posedge clk or negedge rst_n)
if(!rst_n)begin
	data_reg <= 'b0;
end
else if(cnt <= 3'd5)begin
	data_reg <= {data,data_reg[5:1]};
end

always@(posedge clk or negedge rst_n)
if(!rst_n)begin
	match <= 1'b0;
	not_match <= 1'b0;
end
else if(cnt == 3'd5)begin
	if(data_reg == 6'b011100)begin
		match <= 1'b1;
		not_match <= 1'b0;
	end
	else begin
		match <= 1'b0;
		not_match <= 1'b1;
	end
end
else begin
		match <= 1'b0;
		not_match <= 1'b0;
end

endmodule