题解 | 整数倍数据位宽转换8to16

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

reg [15:0] data_r;
reg    cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
	data_r <= 0;
	cnt <= 0;
	valid_out <= 0;
	data_out <= 0;
end else begin
	data_r <= valid_in?{data_r[7:0],data_in}:data_r;
	cnt <= valid_in?cnt+1'b1:cnt;
	if(valid_in && cnt == 'd1)begin
		data_out <= {data_r[7:0],data_in};
		valid_out <= 1;
	end  else begin
		data_out <= data_out;
		valid_out <= 0;

	end
end
end
endmodule