题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0] cnt;
reg div7_p,div7_n;
/*
always@(posedge clk_in or negedge rst)
    if(!rst)
        cnt<=0;
    else
        if(cnt>=6)
            cnt<=0;
        else
            cnt<=cnt+1;

always@(posedge clk_in or negedge rst)
    if(!rst)
        div7_p<=0;
    else
        if(cnt==7/2-1||cnt==6)
            div7_p<=~div7_p;

always@(negedge clk_in or negedge rst)
    if(!rst)
        div7_n<=0;
    else
        if(cnt==7/2-1||cnt==6)
            div7_n<=~div7_n;


assign clk_out7=div7_n&&div7_p;*/

//与分频和或分频的区别在于，与分频的时钟上升沿对齐，或分频的居中对齐。

always@(posedge clk_in or negedge rst)
    if(!rst)
        cnt<=0;
    else
        if(cnt>=6)
            cnt<=0;
        else
            cnt<=cnt+1;

always@(posedge clk_in or negedge rst)
    if(!rst)
        div7_p<=0;
    else
        if(cnt==7/2||cnt==6)
            div7_p<=~div7_p;

always@(negedge clk_in or negedge rst)
    if(!rst)
        div7_n<=0;
    else
        if(cnt==7/2||cnt==6)
            div7_n<=~div7_n;


assign clk_out7=div7_n||div7_p;

endmodule