题解 | #信号发生器#

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [5:0]wave
	);
reg  [5:0] cnt;
wire flag_fang,flag_juchi,flag_sanjiao;
reg [1:0] wave_choise_r;
wire f_change;
//把wave选择存起来，看看选择是否变更
always@ (posedge clk or negedge rst_n)
begin
	if(!rst_n)    wave_choise_r <= 0;
	else  begin wave_choise_r <= wave_choise;  end
end
assign f_change = wave_choise!=wave_choise_r?1:0;
//计时器的正常计数，用flag和wave_choise 来确定如何计数
always@ (posedge clk or negedge rst_n)
begin
	if(!rst_n)
		begin
			cnt <= 0;
			wave <= 0;
		end
	else  if(f_change == 1)
		begin
			case(wave_choise)
			0:	begin cnt <= 0; wave <= 0; end 
			1:  begin cnt <= 0; wave <= 0; end
			2:  begin
					
					
					
					 if(wave>=1) begin cnt = 40 - wave+1;  wave = wave-1 ; end
					else cnt = 40 - wave; 
				end
			endcase
		end
	else if(f_change == 0)
		begin
			case(wave_choise)
			0:	begin 
                wave = flag_fang?0:20; 
                if(wave_choise==0 && cnt == 19) begin cnt<=0; end
                else begin cnt <= cnt + 1 ; end
                
                end 
			1:  begin 
                if(wave_choise==1 && cnt == 20) begin cnt<=0; end
                else begin cnt <= cnt + 1 ; end
                wave <= flag_juchi?0:1+cnt; 
                end
			2:  begin 
                if(wave_choise==2 && cnt == 39) begin cnt<=0; end
                else begin cnt <= cnt + 1 ; end 
			    if(flag_sanjiao)  wave <= wave + 1;
				else	 wave <= wave - 1;			
				end
			endcase
		end
end


assign flag_fang = (cnt>=0 && cnt<9)||cnt==19||cnt==0?1:0;//1时代表空输出，0时代表满输出
assign flag_juchi = (cnt==20)?1:0;//1时代表到顶了，0时代表没有到顶
assign flag_sanjiao = (cnt>=0 && cnt<=19)?1:0;//1时代表着增，0时代表着减，置位的时候也关注一下这里吧。同时设置wave和cnt;
endmodule