题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;

reg [2:0] c_state;
reg [2:0] n_state;
always@(posedge clk or negedge rst) begin
	if(!rst) begin
		c_state <= S0;
	end
	else begin
		c_state <= n_state;
	end
end

always @(*) begin
	if(!rst) begin
		n_state <= S0;
		flag <= 0;
	end
	else begin
		case(c_state) 
			S0: begin n_state <= (data == 1)? S1:S0; flag <= 0; end
			S1: begin n_state <= (data == 1)? S2:S1; flag <= 0; end
			S2: begin n_state <= (data == 1)? S3:S2; flag <= 0; end
			S3: begin n_state <= (data == 1)? S4:S3; flag <= 0; end
			S4: begin n_state <= (data == 1)? S1:S0; flag <= 1; end
		endcase
	end
end


//*************code***********//
endmodule