题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

parameter S0 = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter S3 = 3'd3;
parameter S4 = 3'd4;
//parameter S5 = 3'd5;

reg [2:0] c_state;
reg [2:0] n_state;
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		c_state <= S0;
	end
	else begin
		c_state <= n_state;
	end
end

always @(*) begin
	if(!rst) begin
		n_state <= S0;
	end
	else begin
		case(c_state) 
			S0: n_state <= (data)? S1:S0;
			S1: n_state <= (data)? S1:S2;
			S2: n_state <= (data)? S3:S0;
			S3: n_state <= (data)? S4:S2;
			S4: n_state <= (data)? S1:S2;
			//S5: n_state <= (data)? S3:S0;
			default: n_state <= S0;
		endcase
	end
end

always @(posedge clk or negedge rst) begin//寄存器输出，在序列检测完成下一拍输出检测有效
	if(!rst) begin
		flag <= 0;
	end
	else if(c_state == S4) begin
		flag <= 1;
	end
	else begin
		flag <= 0;
	end
end


//*************code***********//
endmodule