题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,//深度 128
    input [3:0]w_data,
    output reg [3:0]r_data
);
//*************code***********//

//写入数据
reg [3:0] RAM[127:0] ;
always@(posedge clk) begin
    if(enb)
        RAM[addr] <= w_data ;
end

//读出数据  
always@(negedge clk) begin
    if(!rst)
        r_data <= 0 ;
    else if(!enb)
        r_data <= RAM[addr]  ;
    else 
        r_data <= r_data  ;
end
//*************code***********//
endmodule