题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
parameter s0=0;
parameter s1=1;
parameter s2=2;
parameter s3=3;
reg [3:0]state;
reg [3:0]next_state;
always@(posedge clk or negedge rst )begin 
	if(!rst)
	 state<=0;
	 else state<=next_state;
end
always@(*)
begin  if(!rst)
 next_state=s0;
 else case(state)
   s0: next_state=s1;
   s1: next_state=s2;
   s2: next_state=s3;
   s3: next_state=s0;
   default: next_state=s0;
 endcase
 end
 always@(posedge clk or negedge rst )begin 
	if(!rst)
	clk_out<=0;
	else if(state==s0)
	clk_out<=1;
	else clk_out<=0;
 end
//*************code***********//
endmodule