题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter s0=0;
parameter s1=1;
parameter s2=2;
parameter s3=3;
parameter s4=4;

reg[2:0] state;
reg[2:0] next_state;
always@(posedge clk or negedge rst)
begin if(!rst)
   state<=0;
   else 
   state<=next_state;
end

always@(*)
begin 
	case(state)
	s0: if(data) next_state=s1; else next_state=s0; 
	s1: if(data) next_state=s1; else next_state=s2; 
	s2: if(data) next_state=s3; else next_state=s0; 
	s3: if(data) next_state=s4; else next_state=s2; 
	s4: if(data) next_state=s1; else next_state=s2; 
	default: next_state=s0;
	endcase

end
always@(posedge clk or negedge rst)
begin if(!rst)
  flag<=0;
  else if(state==s4)
  flag<=1;
  else 
  flag<=0;
end


//*************code***********//
endmodule