题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg[2:0]cnt; //计数器

//当计数器计数到5时归零
always@(posedge clk or negedge rst_n)
	if(!rst_n) cnt <= 3'd0;
	else if((valid_a)&&(cnt < 3'd5)) cnt <= cnt + 3'd1;
	else if (cnt == 3'd5) cnt <= 3'd0;
	else cnt <= cnt;

//当计数器计数到5时，valid_b信号拉高。
always@(posedge clk or negedge rst_n)
	if(!rst_n) valid_b <= 1'd0;
	else if(cnt == 3'd5) valid_b <= 1'd1;
	else valid_b <= 1'd0;

//当valid_a信号为高电平时，把data_a的值赋给data_b_0
reg[5:0] data_b_0;
always@(posedge clk or negedge rst_n)
	if(!rst_n) data_b_0 <= 6'd0;
	else if(valid_a == 1'd1) data_b_0[cnt] <= data_a;
	else data_b_0 <= data_b_0;

//ready_a信号全程拉高
always@(posedge clk or negedge rst_n)
	if(!rst_n) ready_a <= 1'd0;
	else ready_a <= 1'd1;

//当计数器计数到5时，将data_b_0赋值给data_b
always@(posedge clk or negedge rst_n)
	if(!rst_n) data_b <= 6'd0;
	else if(cnt == 3'd5) data_b <= data_b_0;
	else data_b <= data_b;

endmodule