题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
//data_cnt
reg [1:0] data_cnt;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) data_cnt <= 0;
	else if(valid_in)
		data_cnt <= (data_cnt==2'd2)? 0 : data_cnt+1;
	//else data_cnt <= (valid_in && data_cnt==2'd2)? 0 : data_cnt+1;
end
//data_out
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) data_out <= 0;
	else if(valid_in && (data_cnt==2'd1))
		data_out <= {data_lock,data_in[7:4]};
	else if(valid_in && (data_cnt==2'd2))
		data_out <= {data_lock[3:0],data_in};
end
//data_lock
reg [7:0] data_lock;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) data_lock <= 0;
	else if(valid_in) data_lock <= data_in;
end
//valid_out
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) valid_out <= 0;
	else valid_out <= (valid_in && (data_cnt==2'd1 || data_cnt==2'd2));
end
endmodule

有大佬帮我看看为什么18行注释掉的else结果是不对的吗？data_cnt会提前一个周期计数