题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);

	wire [4:0] g_and0;
	wire [4:0] p_xor0;
	wire [4:0] c_buf;
	wire [15:0] buff;
	wire [4:0] s_xor1;
    genvar i;
	generate 
		for(i=0; i<4; i = i+1) begin
			and and0(g_and0[i], A_in[i], B_in[i]);
			xor xor0(p_xor0[i], A_in[i], B_in[i]);
		end
	endgenerate

	assign c_buf[0] = C_1;
	generate
		for(i=1; i<5; i=i+1) begin
			and and1(buff[i], p_xor0[i-1], c_buf[i-1]);
			or or0(c_buf[i], g_and0[i-1], buff[i]);
			xor xor1(s_xor1[i-1], p_xor0[i-1], c_buf[i-1]);	
		end
	endgenerate

	assign CO = c_buf[4];
	assign S = s_xor1[3:0];
	

endmodule