题解 | #优先编码器电路①#
对题中所给的真值表
,
按位取反后，可以等到Y,I较简单的输入输出关系：
Y0=I9+I7+I5+I3+I1
Y0=I9+I7+I5+I3+I1
Y1=I7+I6+I3+I2
Y2=T7+I6+I3+I2
Y3=I9+I8
计算得到Y后，按位取反得到
`timescale 1ns/1ns
module encoder_0(
input [8:0] I_n ,
output reg [3:0] Y_n
);
wire [8:0] I;
reg [3:0] Y;
assign I =~I_n;
always @ (*) begin
Y[0] = I[8]|I[6]|I[4]|I[2]|I[0];
Y[1] = I[6]|I[5]|I[2]|I[1];
Y[2] = I[6]|I[5]|I[4]|I[3];
Y[3] = I[8]|I[7];
end
always @ (*) begin
Y_n = ~Y;
end
endmodule
#FPGA#module encoder_0(
input [8:0] I_n ,
output reg [3:0] Y_n
);
wire [8:0] I;
reg [3:0] Y;
assign I =~I_n;
always @ (*) begin
Y[0] = I[8]|I[6]|I[4]|I[2]|I[0];
Y[1] = I[6]|I[5]|I[2]|I[1];
Y[2] = I[6]|I[5]|I[4]|I[3];
Y[3] = I[8]|I[7];
end
always @ (*) begin
Y_n = ~Y;
end
endmodule
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