题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
    //method one
    reg [3:0] count;
    reg [8:0] a_data;
    reg flag;
    always@(posedge clk&nbs***bsp;negedge rst_n)begin
        if(!rst_n)begin
            count<=4'd0;
            flag<=1'b0;
            a_data<=9'b0;
        end
        else begin
            if(count==4'd8)begin
                count<=4'd0;
                a_data[count]<=a;
                flag<=1'b1;
            end
            else begin
               count<=count+4'd1;
                a_data[count]<=a;
                flag<=1'b0;
            end
        end              
    end
    wire match_wire;
    assign match_wire=(flag==1'b1)&&(a_data[8:6]==3'b011)&&(a_data[2:0]==3'b110);    
    always@(posedge clk&nbs***bsp;negedge rst_n)
        begin
            if(!rst_n)
                match<=1'b0;
            else
                match<=match_wire;
        end
   /* //method two:FSM coding
   //one hot coding
    parameter IDLE=10'b00_0000_0001;
    parameter S0  =10'b00_0000_0010;
    parameter S1  =10'b00_0000_0100;
    parameter S2  =10'b00_0000_1000;
    parameter S3  =10'b00_0001_0000;
    parameter S4  =10'b00_0010_0000;
    parameter S5  =10'b00_0100_0000;
    parameter S6  =10'b00_1000_0000;
    parameter S7  =10'b01_0000_0000;
    parameter S8  =10'b10_0000_0000;
    //segment one :generate next state
    reg [9:0] cur_state,next_state;
    always@(*)begin
        if(!rst_n)
            next_state=IDLE;
        else begin //data=0_11xx_x110
            case(cur_state)
                IDLE: next_state=(a==1'b0)?S0:IDLE;
                S0  : next_state=(a==1'b1)?S1:S0;
                S1  : next_state=(a==1'b1)?S2:S0;
                S2  : next_state=S3;//x
                S3  : next_state=S4;//x
                S4  : next_state=S5;//x
                S5  : next_state=(a==1'b1)?S6:S0;
                S6  : next_state=(a==1'b1)?S7:S0;
                S7  : next_state=(a==1'b0)?S8:S0;
                S8  : next_state=S0;
                default: next_state=IDLE;
            endcase
        end
    end
    //segment two:generate current state
    always@(posedge clk&nbs***bsp;negedge rst_n)begin
        if(!rst_n)
            cur_state<=IDLE;
        else 
            cur_state<=next_state;        
    end
     //segment three
    wire match_wire;
    assign match_wire=(cur_state==S8);
    always@(posedge clk&nbs***bsp;negedge rst_n)begin
        if(!rst_n)
            match<=1'b0;
        else
            match<=match_wire;        
    end
    */
endmodule