本质上还是借用前面写过的移位寄存器进行比较,不过是加了个counter来卡周期而已 `timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); reg [2:0] cnt; reg [5:0] seq; always@(posedge clk ,negedge rst_n)begin if(!rst_n)begin match<=0; not_match<=0; cnt<=0; seq<=0...