`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); reg [2:0] cnt; reg [5:0] men; always@(posedge clk or negedge rst_n)begin if(!rst_n)begin cnt <= 0; men <= 0; end else if(cnt == 5)begin cnt <= 0; men[5-cnt] <= data; e...