题解 | 脉冲同步电路

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);

    reg data_in_signal;  //打一拍
    reg data_in_signal_r;  //打一拍
    reg data_in_signal_rr;  //打两拍
    reg data_in_signal_rrr; // 边沿检测信号
    reg dataout_signal; // 输出信号反馈
    reg dataout_signal_r; // 输出信号打一拍
    //转电平信号
    always @(posedge clk_fast or negedge rst_n) begin
        if (!rst_n) begin
            data_in_signal <= 1'b0;
        end
        else if(dataout_signal_r == 1'b1) begin
            data_in_signal <= 1'b0; // 反馈信号拉低
        end
        else if(data_in == 1'b1)begin
            data_in_signal <= 1'b1; // 采集快时钟域的输入信号
        end
    end

    //慢时钟域采集电平方案
    always @(posedge clk_slow or negedge rst_n) begin
        if (!rst_n) begin
            {data_in_signal_rrr, data_in_signal_rr, data_in_signal_r} <= {3{1'b0}};
        end
        else begin
            {data_in_signal_rrr, data_in_signal_rr, data_in_signal_r} <= {data_in_signal_rr, data_in_signal_r, data_in_signal}; // 左边给左边，右边给右边
        end
    end

    //慢时钟域边沿检测，得到脉冲信号
    assign dataout = (data_in_signal_rr == 1'b1) && (data_in_signal_rrr == 1'b0); // 上升沿检测, 将data_in_signal_r打一拍

    //快时钟域采集慢时钟域的返回信号
    always @(posedge clk_fast or negedge rst_n) begin
        if (!rst_n) begin
            dataout_signal <= 1'b0;
            dataout_signal_r <= 1'b0;
        end
        else begin
            dataout_signal <= data_in_signal_rr; // 采集慢时钟域的输出信号
            dataout_signal_r <= dataout_signal; // 打一拍
        end
    end
    
endmodule