题解 | 时钟分频（偶数）

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
    reg cnt0;
    reg [1:0] cnt1; // Counter to track clock cycles
    reg [2:0] cnt2; // Counter to track clock cycles

    assign clk_out2 = cnt0; // Output clock toggles every clock cycle
    assign clk_out4 = cnt1[1]; // Output clock toggles every 2 clock cycles
    assign clk_out8 = cnt2[2]; // Output clock toggles every 4 clock cycles

    always @(posedge clk_in or negedge rst) begin
        if (!rst) begin
            cnt0 <= 'b0;
            cnt1 <= 'b00;
            cnt2 <= 'b000;
        end else begin
            cnt0 <= cnt0 + 1'b1; // Toggle every clock cycle
            cnt1 <= cnt1 - 1'b1;
            cnt2 <= cnt2 - 1'b1;
        end
    end

//*************code***********//
endmodule