题解 | #脉冲同步电路#

`timescale 1ns/1ns
module pulse_detect
(
    clk_fast  ,
    clk_slow  ,
    rst_n     ,
    data_in   ,

    dataout
);

    input     clk_fast    ;
    input     clk_slow    ;
    input     rst_n       ;
    input     data_in     ;
    output    dataout     ;

    // 快时钟域下信号扩展周期数，并进行再次打拍
    reg       buf1_data_in;
    reg       buf2_data_in;
    always @ (posedge clk_fast, negedge rst_n)
    begin
        if (rst_n==1'b0)
        begin
            buf1_data_in <= 1'b0;
            buf2_data_in <= 1'b0;
        end
        else 
        begin
            buf1_data_in <= data_in;
            buf2_data_in <= buf1_data_in;
        end
    end
    wire      ex_data_in  ;
    reg       buf_ex_din  ;
    assign ex_data_in = buf1_data_in|buf2_data_in;
    always @ (posedge clk_fast, negedge rst_n)
    begin
        if (rst_n==1'b0)
        begin
            buf_ex_din <= 1'b0;
        end
        else
        begin
            buf_ex_din <= ex_data_in;
        end
    end

    // 将扩展后的信号同步到慢时钟域；多打一拍做边沿检测
    reg       syn_ex_din;
    reg       dly1_syn_ex_din;
    reg       dly2_syn_ex_din;
    always @ (posedge clk_slow, negedge rst_n)
    begin
        if (rst_n==1'b0)
        begin
            syn_ex_din      <= 1'b0;
            dly1_syn_ex_din <= 1'b0;
            dly2_syn_ex_din <= 1'b0;

        end
        else
        begin
            syn_ex_din      <= buf_ex_din      ;
            dly1_syn_ex_din <= syn_ex_din      ;
            dly2_syn_ex_din <= dly1_syn_ex_din ;
        end
    end

    // 边沿检测，确保得到的输出脉冲只有一个周期
    assign dataout = dly1_syn_ex_din&(~dly2_syn_ex_din);
    
endmodule //pulse_detect