题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [1:0] count;
reg [7:0] d_reg;
always@(posedge clk or negedge rst) begin
    if(~rst) begin
        count<=0;
        out<=0;
        d_reg<=0;
        input_grant<=1'b0;
    end
    else begin
        count<=count+1;
        case(count)
            2'b00:begin
                out<=d;
                d_reg<=d;
                input_grant<=1'b1;
            end
            2'b01:begin
                
                out<=d_reg+(d_reg<<1);
                input_grant<=1'b0;
            end
            2'b10:begin
                out<=d_reg+(d_reg<<2)+(d_reg<<1);
                input_grant<=1'b0;
            end
            2'b11:begin
                out<=d_reg<<3;
                input_grant<=1'b0;
            end
        endcase
    end
end




//*************code***********//
endmodule