题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);



reg         data_in_latch       ;

reg         data_in_latch_r1    ;
reg         data_in_latch_r2    ;
reg         data_in_latch_r3    ;

//data_in_latch
always @(posedge clk_fast or negedge rst_n)
begin
    if(!rst_n)
        data_in_latch <= 1'b0   ;
    else if(dataout) //回落
        data_in_latch <= 1'b0   ;
    else if(data_in) //拉高
        data_in_latch <= 1'b1   ;
end

//data_in_latch 在clk_slow中打拍
always @(posedge clk_slow or negedge rst_n)
begin
    if(!rst_n) 
    begin
        data_in_latch_r1 <= 1'b0    ;
        data_in_latch_r2 <= 1'b0    ;
        data_in_latch_r1 <= 1'b0    ;
    end
    else
    begin
        data_in_latch_r1 <= data_in_latch   ;
        data_in_latch_r2 <= data_in_latch_r1;
        data_in_latch_r3 <= data_in_latch_r2;
    end
end

//dataout
assign dataout = data_in_latch_r2 & !data_in_latch_r3   ;

endmodule