题解 | #数据串转并电路#

`timescale 1ns/1ns
module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
// always@(*)begin
//     ready_a = 1'b1;
// end
// assign ready_a = 1'b1;

reg [2:0]   counter     ;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        counter <= 3'b0;
        ready_a <= 1'b0;
        // data_b <= 6'b0;
    end
    else if(valid_a == 1) begin
        if(counter == 3'b101) begin
            counter <= 3'b0;
            ready_a <= 1'b1;
        end
        else begin
            counter <= counter + 1'b1;
            ready_a <= 1'b1;
        end
    end
    else begin
        counter <= counter;
        ready_a <= 1'b1;
    end
end

reg [5:0]  data_temp       ;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        data_temp <= 6'b0;
        // data_b <= 6'b0;
    end
    // else if(counter == 3'b101)begin
    //     data_temp <= {data_a,data_temp[5:1]};
    //     data_b <= data_temp;
    // end
    else if(valid_a)  begin
        data_temp <= {data_a,data_temp[5:1]};
        // data_b <= data_b;
    end
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_b <= 6'b0;
    else if(counter == 3'd5)
        data_b <= {data_a,data_temp[5:1]};
end


always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        valid_b <= 1'b0;
    else if(counter == 3'b101 && valid_b == 0)
        valid_b <= 1'b1;
    else 
        valid_b <= 1'b0;
end
endmodule

可以提前一个cycle输出temp数据