题解 | #任意奇数倍时钟分频#

`timescale 1ns/1ns

module clk_divider
    #(parameter dividor = 5)
( 	input clk_in,
	input rst_n,
	output clk_out
);
parameter CNT_WIDTH = $clog2(dividor);
reg [CNT_WIDTH+1:0]cnt;
always@(posedge clk_in or negedge rst_n or negedge clk_in )
begin
	if(!rst_n)cnt<=0;
	else begin
		if(cnt==2*dividor-1)cnt<=0;
		else cnt<=cnt+1;
	end
end  
reg clk_out_reg;
always@(posedge clk_in  or negedge rst_n or negedge clk_in )
begin
	if(!rst_n)clk_out_reg<=0;
	else begin
		if(cnt==dividor-2| cnt==2*dividor-2)clk_out_reg<=(~clk_out_reg);
		else clk_out_reg<=clk_out_reg;//复位信号撤销后要求cnt=3时就改变波形
	end
end
assign clk_out=clk_out_reg;
endmodule