题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
reg [3:0]state,next_state;
parameter s0 = 0;
parameter s1 = 1;
parameter s2 = 2;
parameter s3 = 3;
parameter s4 = 4;
parameter inv = 5;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		match<=0;
		state<=0;
		next_state<=0;
	end
	else begin
		state<=next_state;
		match <= (next_state==s4);
	end

end
always@(*)begin
	next_state =state;
	case(state)
	s0: next_state = (data==0) & (data_valid==1) ? s1 : (data_valid==0 ? s0 : s0);
	s1: next_state = (data==1) & (data_valid==1) ? s2 : (data_valid==0 ? s1 : s1);
	s2: next_state = (data==1) & (data_valid==1) ? s3 : (data_valid==0 ? s1 : s1);
	s3: next_state = (data==0) & (data_valid==1) ? s4 : (data_valid==0 ? s0 : s0);
	s4: next_state = (data==1) & (data_valid==1) ? s2 : (data_valid==0 ? s1 : s1);
	default: next_state = s0;
	endcase
end
endmodule