题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
reg [1:0] cnt;
always@(posedge clk or negedge rst)
  if(!rst)
    cnt <= 2'd0;
  else if(cnt==2'd3)
    cnt <= 2'd0;
  else  
    cnt <= cnt + 2'd1;

always@(posedge clk or negedge rst)
  if(!rst)
    clk_out <= 1'b0;
  else if(rst && cnt==2'd0)
    clk_out <= 1'd1;
  else 
    clk_out <= 1'd0;



//*************code***********//
endmodule