题解 | #根据状态转移表实现时序电路#
根据状态转移表实现时序电路
https://www.nowcoder.com/practice/455c911bee0741bf8544a75d958425f7
`timescale 1ns/1ns
module seq_circuit(
input A ,
input clk ,
input rst_n,
output wire Y
);
reg [1:0] q;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
q <= 2'b00;
end
else if(A)
q <= q - 1;
else
q <= q + 1;
end
assign Y = (q == 2'b11);
endmodule
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