题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
parameter S0 = 3'd0;
parameter S0_5 = 3'd1;
parameter S1 = 3'd2;
parameter S1_5 = 3'd3;
parameter S2 = 3'd4;
parameter S2_5 = 3'd5;
parameter S3 = 3'd6;


reg [2:0] c_state;
reg [2:0] n_state;
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		c_state <= 0;
	end
	else begin
		c_state <= n_state;
	end
end

always@(*) begin
	if(!rst) begin
		n_state <= 0;
	end
	else begin
		 case(c_state)
            S0     : n_state = d1? S0_5:
                              d2? S1:
                              n_state;
            S0_5   : n_state = d1? S1:
                              d2? S1_5:
                              n_state;
            S1     : n_state = d1? S1_5:
                              d2? S2:
                              n_state;
            S1_5   : n_state = ~sel? S0:
                              d1? S2:
                              d2? S2_5:
                              n_state;
            S2     : n_state = ~sel? S0:
                              d1? S2_5:
                              d2? S3:
                              n_state;
            default: n_state = S0;
        endcase
	end
end

always@(*) begin
	if(~rst) begin
		{out1, out2, out3} = 3'b000;
	end
	else begin
		case(c_state)
			S0, S0_5, S1: {out1, out2, out3} = 0;
			S1_5        : {out1, out2, out3} = ~sel? 3'b100: 3'b000;
			S2          : {out1, out2, out3} = ~sel? 3'b101: 3'b000;
			S2_5        : {out1, out2, out3} = ~sel? 3'b101: 3'b010;
			S3          : {out1, out2, out3} = ~sel? 3'b101: 3'b011;
			default     : {out1, out2, out3} = 3'b000;
		endcase
	end
end





//*************code***********//
endmodule