题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;

reg [1:0] c_state;
reg [1:0] n_state;
always@(posedge clk or negedge rst) begin
	if(!rst) begin
		c_state <= S0;
	end
	else begin
		c_state <= n_state;
	end
end

always @(*) begin
	if(!rst) begin
		n_state <= S0;
	end
	else begin
		case(c_state) 
			S0: n_state <= (data == 1)? S1:S0;
			S1: n_state <= (data == 1)? S2:S1;
			S2: n_state <= (data == 1)? S3:S2;
			S3: n_state <= (data == 1)? S0:S3;
		endcase
	end
end

always @(posedge clk or negedge rst) begin
	if(!rst) begin
		flag <= 0;
	end
	else if (c_state == S3 && data == 1) begin
		flag <= 1;
	end
	else begin
		flag <= 0;
	end
end



//*************code***********//
endmodule