题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);

//*************code***********//

parameter S0 = 5'b00001 ;
parameter S1 = 5'b10000 ;
parameter S2 = 5'b01000 ;
parameter S3 = 5'b00100 ;
parameter S4 = 5'b00010 ;

reg [4:0] Cur_state ;
reg [4:0] Nxt_state ;

reg Y_reg ;
//第一段式
always@(posedge clk or negedge rst_n)  begin
	if(!rst_n)
		Cur_state <= S0 ;
	else
		Cur_state <= Nxt_state ;
end

//第二段式
always@(*) begin
	if(!rst_n) begin
		Y_reg = 0;
		Nxt_state = S0 ;
	end
	else	
		case(Cur_state)
		S0:if(din == 0) begin
			Y_reg = 0;
			Nxt_state = S0 ;
		end 
		else begin
			Y_reg = 0;
			Nxt_state = S1 ;
		end

		S1:if(din == 0) begin
			Y_reg = 0;
			Nxt_state = S0 ;
		end 
		else begin
			Y_reg = 0;
			Nxt_state = S2 ;
		end

		S2:if(din == 0) begin
			Y_reg = 0;
			Nxt_state = S3 ;
		end 
		else begin
			Y_reg = 0;
			Nxt_state = S1 ;
		end

		S3:if(din == 0) begin
			Y_reg = 0;
			Nxt_state = S3 ;
		end 
		else begin
			Y_reg = 0;
			Nxt_state = S4 ;
		end

		S4:if(din == 0) begin
			Y_reg = 0;
			Nxt_state = S0 ;
		end 
		else begin
			Y_reg = 1;
			Nxt_state = S0 ;
		end
		default: Nxt_state = S0 ;
		endcase
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		Y <= 'd0;
	else 
        Y <= Y_reg;       
end

endmodule