题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

reg  cnt ;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		cnt <= 'd0;
	else if (valid_in)
		cnt <= cnt + 'd1 ;
	else 
		cnt <= cnt ;
end

//valid_out
always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		valid_out <= 'd0;
	else if (valid_in && cnt == 'd1)
		valid_out <= 'd1 ;
	else 
		valid_out <= 'd0 ; 
end

reg [15:0] data_reg ;
always@(posedge clk or negedge rst_n)  begin
	if(!rst_n) 
		data_reg <= 0 ;
	else if(valid_in && cnt == 'd0) 
		data_reg[15:8] <= data_in ;
	else if(valid_in && cnt == 'd1)
		data_out <= {data_reg[15:8], data_in} ;
end

//data_out
always@(posedge clk or negedge rst_n)  begin
	if(!rst_n) 
		data_out <= 0 ;
	else if(valid_in && cnt == 'd1)
		data_out <= {data_reg[15:8], data_in} ;
end

endmodule