题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

parameter S0 = 5'b00001 ;
parameter S1 = 5'b10000 ;
parameter S2 = 5'b01000 ;
parameter S3 = 5'b00100 ;
parameter S4 = 5'b00010 ;

reg flag_reg ;
reg [4:0] Cur_state ;
reg [4:0] Nxt_state ;

//第一段式
always@(posedge clk or negedge rst)  begin
	if(!rst)
		Cur_state <= S0 ;
	else
		Cur_state <= Nxt_state ;
end

//第二段式
always@(*) begin
	if(!rst) begin

		Nxt_state = S0 ;
	end
	else	
		case(Cur_state)
		S0:if(data == 1) begin

			Nxt_state = S1 ;
		end 
		else begin

			Nxt_state = S0 ;
		end

		S1:if(data == 0) begin  //1

			Nxt_state = S2 ;
		end 
		else begin

			Nxt_state = S1 ;
		end

		S2:if(data == 1) begin //0
	
			Nxt_state = S3 ;
		end 
		else begin
	
			Nxt_state = S0 ;
		end

		S3:if(data == 1) begin //1
	
			Nxt_state = S1 ;
		end 
		else begin
	
			Nxt_state = S2 ;
		end

		default: Nxt_state = S0 ;
		endcase
end

always@(posedge clk or negedge rst)  begin
	if(!rst)
		flag_reg <= 0 ;
	else if(Cur_state == S3) begin
		if(data==1)
			flag_reg <= 1 ;
		else 
			flag_reg <= 0 ;
	end
	else 
		flag_reg <= 0 ;
end

always@(posedge clk or negedge rst)  begin
	if(!rst)
		flag <= 0 ;
	else if(flag_reg == 1) 
		flag <= 1 ;
	else 
		flag <= 0 ;
end

//*************code***********//
endmodule