题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);


reg [1:0] Cur_state ;
reg [1:0] Nxt_state ;
reg y;
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        Cur_state <= 0;
    end
    else 
        Cur_state <= Nxt_state ;
end

always@(* ) begin
    case(Cur_state)
        2'b00:if(C==0) begin
                Nxt_state = 2'b00 ;
                y = 0;
            end
              else begin
                Nxt_state = 2'b01 ;
                y=0;
              end
        
        2'b01:if(C==0) begin
                Nxt_state = 2'b11 ;
                y = 0;
            end
              else begin
                Nxt_state = 2'b01 ;
                y=0;
              end
        
        2'b11:if(C==0) begin
                Nxt_state = 2'b11 ;
                y = 1;
            end
              else begin
                Nxt_state = 2'b10 ;
                y=1;
              end
        
        2'b10:if(C==0) begin
                Nxt_state = 2'b00 ;
                y = 0;
            end
              else begin
                Nxt_state = 2'b10 ;
                y=1;
              end
    endcase

end



assign Y = y ;


endmodule