题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,

	output reg match
);

parameter s0 = 5'b00001;
parameter s1 = 5'b00010;
parameter s2 = 5'b00100;
parameter s3 = 5'b01000;
parameter s4 = 5'b10000;

reg [4:0]statue;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    statue <= s1;
	else if (data_valid == 1'b1)
	    begin
			case (statue) 
			    s0 : if (data == 1'b1)
				        statue <= s0;
					else 
					    statue <= s1;
				s1 : if (data == 1'b1)
				        statue <= s2;
					else 
					    statue <= s1;
				s2 : if (data == 1'b1)
				        statue <= s3;
					else 
					    statue <= s1;
				s3 : if (data == 1'b1)
				        statue <= s0;
					else
					    statue <= s4;
				s4 : if (data == 1'b1)
				        statue <= s2;
					else 
					    statue <= s1;
				default : statue <= s0;
			endcase
		end

always@(*)
    if (rst_n == 1'b0)
	    match <= 1'b0;
	else if (statue == s4 && data_valid == 1'b1)
		match <= 1'b1;
	else 
	    match <= 1'b0;

endmodule