题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);
parameter s0=0;
parameter s1=1;
parameter s2=2;
parameter s3=3;
parameter s4=4; 
reg[3:0]state;
reg [3:0]next_state;
always@(posedge clk or negedge rst_n)
begin if(!rst_n)
  state<=0;
else state<=next_state;
end
always@(*)
begin if(!rst_n)
next_state=0;
else case(state)
   s0:if(din) next_state=s1; else next_state=s0;
   s1:if(din) next_state=s2; else next_state=s0;
   s2:if(din==0) next_state=s3; else next_state=s2;
   s3:if(din) next_state=s4; else next_state=s0;
   s4:if(din) next_state=s1; else next_state=s0;
   default:next_state=0;
endcase
end
always@(posedge clk or negedge rst_n)
begin if(!rst_n)
Y<=0;
else if(state==s4)
Y<=1;
else 
Y<=0;
end 
endmodule