题解 | #同步FIFO#

`timescale 1ns/1ns

/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  
	,input [WIDTH-1:0] wdata      	
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  
	,output reg [WIDTH-1:0] rdata 		
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output 			reg	wfull	,
	output 		    reg	rempty	,
	output reg [WIDTH-1:0]	rdata
);
reg [3:0] w_ptr;
reg [3:0] r_ptr;
reg [WIDTH-1:0]buff[DEPTH-1:0];
reg [4:0]num;
always@(posedge clk or negedge rst_n)
begin if(!rst_n)
      begin wfull<=0;
	  rempty<=0;end
	  else if(num==0)
	  rempty<=1;
	  else if (num==DEPTH)
	  wfull<=1;
	  else begin wfull<=0;
	  rempty<=0;end
end

always@(posedge clk or negedge rst_n)
begin if(!rst_n)
      begin w_ptr<=0;
	  num<=0; end 
	  else if(winc&(!wfull))
	   begin w_ptr<=w_ptr+1;
	   num<=num+1;
	   buff[w_ptr]<=wdata;
	   end
end
always@(posedge clk or negedge rst_n)
begin if(!rst_n)
      begin r_ptr<=0;
	  end 
	  else if(rinc&(!rempty))
	   begin r_ptr<=r_ptr+1;
	   num<=num-1;
	   rdata<=buff[r_ptr];
	   end
end 
endmodule