题解 | #信号顺序调整#

`timescale 1ns/1ns

module top_module(
    input    wire    [12:0] in ,
    output   wire    [12:0] out
);
    wire [3:0] a,b,c,d;
    assign {a,b,c,d} = in;
    assign out = {d,c,b,a};
endmodule