题解 | #输入序列不连续的序列检测#未使用fsm

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
// 0110
reg [3:0] data_ray;
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        match <= 0;
        data_ray <= 0;
    end
    else begin
        if (data_valid)
            data_ray <= {data_ray[2:0],data};
			if (data_ray[2:0]==3'b011&& (~data))
				match <= 1;
        if (match)
            match <= 0;
    end
end

  
endmodule

match的时序需提前一个时钟周期