题解 | #不重叠序列检测#

1. FSM；
2. 六个状态，s0,s1,s2,s3,s4,s5;
3. 一个计数器cnt，从0计数到5；
4. 状态转移条件按照题意011100决定；
5. 计数器为0时进入s0状态，计数器为5时，判断状态是否在s5，是就是想要的序列，否则不是。

/*********************************************************************************************
Module Name: sequence_no 
Description: 检测的序列为011100
Time/Edition/Editor:
    2023.4.27/v1.0/HouXin
*********************************************************************************************/

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
//定义各个状态
	parameter s0 	= 5'd0;
	parameter s1 	= 5'd1;
	parameter s2 	= 5'd2;
	parameter s3 	= 5'd3;
	parameter s4 	= 5'd4;
	parameter s5 	= 5'd5;

	
	reg [6:0]curr_state;
	reg [6:0]next_state;
//计数器：cnt
	reg [3:0] cnt;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			cnt <= 4'd0;
		end
		else if (cnt == 4'd5)begin
			cnt <= 4'd0;
		end
		else begin
			cnt <= cnt +  1'b1;
		end
	end
	
//FSM one step 
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			curr_state <= s0;
		end
		else begin
			curr_state <= next_state;
		end
	end

//FSM second step  011100
	always@(*)begin
		case(curr_state)
			s0:
				if(cnt == 4'd0)begin
					if(data==0)begin
						next_state = s1;	//0
					end
					else begin
						next_state = s0;
					end
				end
			s1: 
				if(data==1)begin
					next_state = s2;	//1
				end
				else begin
					next_state = s0;
				end
			s2:
				if(data==1)begin
					next_state = s3;	//1
				end
				else begin
					next_state = s0;
				end
			s3:
				if(data==1)begin
					next_state = s4;	//1
				end
				else begin
					next_state = s0;	
				end
			s4: 
				if(data===0)begin
					next_state = s5;	//0
				end
				else begin
					next_state = s0;	
				end	
			s5: 
				if(data===0)begin
					next_state = s5;	//0
				end
				else begin
					next_state = s0;	
				end	
			default:next_state = s0;
		endcase
	end
	// FSM 3 step
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			match 		<= 1'b0;
			not_match	<= 1'b0;
		end
		else if(cnt==4'd5) begin
			if(curr_state == s5)begin
				match 		<= 1'b1;
				not_match	<= 1'b0;
			end
			else	begin
				match 		<= 1'b0;
				not_match	<= 1'b1;
			end
		end
		else 	begin
				match 		<= 1'b0;
				not_match	<= 1'b0;
		end
	end

	
endmodule