题解 | #Johnson Counter#

//Q<={~Q[0],Q[3:1]};
`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
parameter s0=4'b0000,s1=4'b1000,s2=4'b1100,s3=4'b1110,s4=4'b1111,
s5=0111,s6=4'b0011,s7=4'b0001;

reg [3:0]     state;
reg [3:0]     next_state;

   always@(posedge clk or negedge rst_n)
   begin
    if(!rst_n)
    Q<=0;
    else
    Q<={~Q[0],Q[3:1]};
   end
   

endmodule