题解 | #格雷码计数器#

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
reg [3:0] bit_num;
reg flag;

always@(posedge clk or negedge rst_n)  begin
    if(!rst_n)
        flag <= 1'b0;
    else
        flag <= ~flag;
end
always@(posedge flag or negedge rst_n)  begin
    if(!rst_n)
        bit_num <= 'd0;
    else
        bit_num <= bit_num + 1'b1;
end
always@(posedge clk or negedge rst_n)  begin
    if(!rst_n)
        gray_out <= 'd0;
    else
        gray_out <= bit_num ^(bit_num >> 1);
end
//assign gray_out = bit_num;
endmodule