题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
localparam DEPTH = 8,
			WIDTH = 4;
integer i;
reg [WIDTH-1:0] mem [DEPTH-1:0];
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		for(i=0;i<DEPTH;i=i+1) mem[i] <= 0;
	end
	else if(write_en) mem[write_addr] <= write_data;
end
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) read_data <= 0;
	else if(read_en) read_data <= mem[read_addr];
end
endmodule