题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
    reg [3:0] mem [127:0];
    integer i;
    
    always @(posedge clk or negedge rst) begin
        if(rst == 1'b0)begin
            for(i=0;i<128;i=i+1)begin
                mem[i] <= 'd0;
            end
        end
        else if(enb)
            mem[addr] <= w_data;
        else
            mem[addr] <= mem[addr];
    end

    assign r_data = (enb == 1'b0) ? mem[addr] : 4'd0;

//*************code***********//
endmodule